The present invention relates to a step-down voltage output circuit for use in a semiconductor integrated circuit.
Referring to FIG. 7, FIG. 8, and FIG. 9, a step-down voltage output circuit using a charge pump circuit of a prior art will be described. FIG. 7 is a block diagram showing a configuration of the step-down voltage output circuit using the charge pump circuit of the prior art.
In FIG. 7, the step-down voltage output circuit using the charge pump circuit of the prior art includes an oscillating circuit 1 that oscillates at a predetermined frequency and outputs a clock signal V1, a control logic 2 that receives the clock signal V1 as an input signal, a P-channel MOS transistor M1, an N-channel MOS transistor M2, an N-channel MOS transistor M3, an N-channel MOS transistor M4 (hereinafter referred to as “an M1”, “an M2”, “an M3”, and “an M4” for simplicity, respectively), a capacitor 7 with a capacitance of C1, a power-supply voltage applying terminal 9 (hereinafter referred to as “a Vcc terminal 9”) and a step-down voltage output terminal 10 (hereinafter referred to as “a Vsub terminal 10”). In addition, the power-supply voltage, which is applied to the Vcc terminal 9, is defined as Vcc, and the step-down voltage, which is output from the Vsub terminal 10, is defined as Vsub.
As to the oscillating circuit 1, an input terminal thereof is connected to the Vcc terminal 9, an output terminal thereof is connected to the control logic 2, respectively. As to the control logic 2, one input terminal thereof is connected to the Vcc terminal 9, the other input terminal thereof is connected to the output terminal of the oscillating circuit 1, one of the output terminals thereof is connected to a gate of the M1, another output terminal thereof is connected to a gate of the M2, and the other output terminal thereof is connected to a gate of the M3 and a gate of the M4, respectively. As to the M1, the gate thereof is connected to one of the output terminals of the control logic 2, a source thereof is connected to the Vcc terminal 9, and a drain thereof is connected to one electrode of the capacitor 7, respectively. As to the M2, the gate thereof is connected to another output terminal of the control logic 2, a source thereof is connected to the ground (hereinafter referred to as “GND”), and a drain thereof is connected to the other electrode of the capacitor 7, respectively. As to the M3, the gate thereof is connected to the other output terminal of the control logic 2, a source thereof is connected to one electrode of the capacitor 7, and a drain thereof is connected to GND, respectively. As to the M4, the gate thereof is connected to the other output terminal of the control logic 2, a source thereof is connected to the Vsub terminal 10, and a drain thereof is connected to the other electrode of the capacitor 7, respectively. As to the capacitor 7, one electrode thereof is connected to the drain of the M1 and the source of the M3, and the other electrode is connected to the drain of the M2 and the drain of the M4, respectively.
The control logic 2 is configured as shown in FIG. 8, for example. The control logic 2 receives the clock signal V1 from the oscillating circuit 1 through the control logic input terminal 70. The control logic 2 outputs the signals V2, V3 and V4 for controlling ON (an operating state, or a conductive state between the source and the drain of a transistor) and OFF (a NON-operating state, or a NON-conductive state between the source and the drain of a transistor) of the M1, the M2, and the M3 and the M4, respectively, to the control logic output terminals 71, 72 and 73.
FIG. 9 is a timing diagram showing the operations of the step-down voltage output circuit using a charge pump circuit of the prior art. In FIG. 9, a period in which the signal V2 is LOW, the signal V3 is HIGH, and the signal V4 is LOW is defined as period T1. A period in which the signal V2 is HIGH, the signal V3 is LOW, and the signal V4 is HIGH is defined as period T2. A period in which the signal V2 is HIGH, the signal V3 is LOW, and the signal V4 is LOW is defined as period T3. In the step-down voltage output circuit configured as shown in FIG. 7, the operation timings, each operation timing whereof is formed as one cycle of T3→T1→T3→T2→T3 constituted by the above-mentioned periods T1, T2, and T3, are repeated. Thereby, the step-down voltage output voltage Vsub is generated at the Vsub terminal 10. Each period T1, T2 and T3 will be described below with reference to FIGS. 7, 8 and 9.
First of all, the oscillating circuit 1 starts self-oscillation and outputs the clock signal V1 when the power-supply voltage Vcc is applied to the input terminal thereof. The control logic 2 receives the clock signal V1 as an input signal, and outputs signals V2, V3, and V4 for respectively controlling ON and OFF of the M1, the M2, and the M3 and the M4.
During the period T1, the M1 is turned ON (conductive), the M2 is turned ON (conductive), and the M3 and the M4 are turned OFF (NON-conductive) since the signal V2 is LOW, the signal V3 is HIGH, and the signal V4 is LOW.
In this state, one electrode of the capacitor 7 is connected to the Vcc terminal 9, and the other electrode thereof is connected to GND. The capacitor 7 is charged with a time constant determined by an ON resistance RONM1 of the M1 (a resistance between the drain and the source of the M1 when the M1 is ON) and the capacitance C1 of the capacitor 7. (Hereinafter the voltage charged in the capacitor 7 is referred to as “VC”). It is preferred that the control is executed so that the voltage VC is equal to the power-supply voltage Vcc. Therefore, the transistor size of the M1 needs to be decided so that the time constant is much shorter than the period T1.
During the period T2, the M1 is turned OFF (NON-conductive), the M2 is turned OFF (NON-conductive), and the M3 and the M4 are turned ON (conductive) since the signal V2 is HIGH, the signal V3 is LOW, and the signal V4 is HIGH.
In this state, one electrode of the capacitor 7 is connected to GND, and the other electrode thereof is connected to the Vsub terminal 10. Therefore, the voltage VC charged in the capacitor 7 during the period T1 is discharged, and then the discharging voltage −VC of the capacitor 7, which is equal to a negative power-supply voltage −Vcc, is output to the Vsub terminal 10.
During the period T3, the M1, the M2, the M3 and the M4 are all turned OFF (NON-conductive) since the signal V2 is HIGH, the signal V3 is LOW, and the signal V4 is LOW.
Due to the effect of parasitic capacitance consisted between the gate electrodes of the M1 and the M3 and substrate, the switching from LOW to HIGH in the signal V2 and the switching from HIGH to LOW in the signal V4 are possibly delayed. If the period T1, in which the signal V2 is LOW, and the period T2, in which the signal V4 is HIGH, are made to come close each other, both of the M1 and the M3 might be ON simultaneously, and as a result, a pass-through current might flow between Vcc potential and GND potential.
In the step-down voltage output circuit using the charge pump circuit of the prior art, by interposing the period T3 for temporarily turning OFF all of the transistors between the period T1 and the period T2, incidence of the above-mentioned pass-through current is prevented.
In addition, the length of the period T3 is determined depending on delay time of the clock signal V1 that is determined by a resistance 21 and a capacitor 22 in the control logic 2 shown in FIG. 8.
In the case that a semiconductor integrated circuit incorporates therein such a step-down voltage output circuit and supplies a substrate potential from the Vsub terminal 10, the load circuit connected to the Vsub terminal 10 can receive the negative power-supply voltage −Vcc as well as the positive power-supply voltage Vcc. For example, in the case that an audio circuit is connected to the Vsub terminal 10 as a load, an output dynamic range of the audio circuit that receives the positive and negative power-supply voltages Vcc and −Vcc becomes larger twice as much as that of the circuit that receives the positive power-supply voltage Vcc and the ground potential GND.
However, in the step-down voltage output circuit using the charge pump circuit of the prior art described above, in the case that the Vsub terminal 10 is connected to a substrate potential of another circuit, there causes a certain time of delay in outputting of the clock signal V1 at a predetermined amplitude from the oscillating circuit 1 after activation of the power-supply voltage Vcc. During the period between the time of activation of the power supply Vcc and the time when the oscillating circuit 1 outputs the clock signal V1 at the predetermined amplitude and the charge pump circuit is completely operated in compliance with the clock signal V1, the step-down voltage generated at the Vsub terminal 10 is kept to a low voltage close to GND potential. In addition, during this period the Vsub terminal 10 is connected to the drain of the M4. Therefore, the output impedance at the Vsub terminal 10 becomes high and the substrate potential connected to the Vsub terminal 10 might get unstable. As a result, a virtual thyristor formed of parasitic elements on the load circuit connected to the Vsub terminal 10 might be activated. The step-down voltage output circuit using the charge pump circuit of the prior art has a problem that activation of the virtual thyristor tends to cause breakdown of the circuit, that is, so-called latch-up phenomenon.
Furthermore, in the step-down voltage output circuit using the charge pump circuit of the prior art, when the step-down voltage output at the Vsub terminal 10 is changed from ON state to OFF state (from −Vcc potential to GND potential), the substrate potential changes rapidly. Therefore, the step-down voltage output circuit using the charge pump circuit of the prior art has a problem that the load circuit connected to the Vsub terminal 10 might be damaged due to rapid change of the substrate potential.